MRO Magazine

Research and Markets: AMD High-Bandwidth Memory – Reverse Costing Analysis

September 11, 2015
By Business Wire News


Research and Markets ( has announced the addition of the “AMD High-Bandwidth Memory – Reverse Costing Analysis” report to their offering.

This industry is proud to release a complete report on the world’s first HBM integrated on chip featured in the latest AMD graphic card Radeon R9 Fury X. Led by AMD and SK Hynix, this 3D & 2.5D component integrates HBM memories (DRAM dies & Logic dies connected with via-middle TSV and micro-bumps) and GPU stacked onto a silicon interposer (including also via-middle TSV).

The HBM delivers 60% more memory bandwidth, 3x the performance per watt and consumes 94% less PCB area than GDDR5.

The report includes a complete physical analysis of the packaging process, with details on all technical choices regarding process and equipment (wafer bonding, via etching, via filling, bumping, underfill) and materials.

Also, the complete manufacturing supply chain has been identified (GPU foundry, Interposer foundry, HBM Foundry, PCB substrate manufacturer, OSAT product integrator) in order to provide a detailed description of the manufacturing process with manufacturing cost calculation.

The report also features a comparison with Samsung 3D TSV DRAM stacking process in order to understand the different technology choices made by the different players.

Key Topics Covered:

1. Introduction

2. Physical Analysis

– Physical Analysis Methodology

– AMD Graphic Card Teardown

– Graphic Card Opening

– Package

– View, Dimensions & Marking

– Dies Size

– DRAM Die

– View, Dimensions & Marking

– µBumps & TSVs

– Logic Die

– View, Dimensions & Marking

– µBumps & TSVs

– Cross-Section

– Package Cross-Section

– PCB & Frame Cross-Section

– Interposer Cross-Section

– GPU µBumps Cross-Section

– HBM Stack Cross-Section (Side Mold, µBumps, Underfill, TSV)

– Comparison with Samsung 3D TSV DRAM stacking process

3. Manufacturing Process Flow

– Global Overview

– GPU Process Description & Foundry

– Interposer Process Flow & Foundry

– HBM Stack Process Flow (TSV & TCB) & Foundry

– Flip-Chip & Stacking Process Flow & Assembly Unit

4. Cost Analysis

– Main steps of economic analysis

– Yields Hypotheses

– GPU Front-End & Die Cost

– Interposer Wafer & Die Cost

– DRAM Front-End Cost

– TSV Manufacturing Cost

– TSV Manufacturing Cost per Process Steps

– Micro-Bumping Manufacturing Cost

– Micro-Bumping Cost per Process Steps

– DRAM Die Cost

– Logic Die Cost

– HBM Stack Cost

– Final Assembly Manufacturing Cost

– Final Component Cost

For more information visit

Research and Markets
Laura Wood, Senior Manager
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Sector: Computing and Technology