DVCon U.S. 2016 Announces Call for Extended Abstracts

LOUISVILLE, Colo.

The 2016 Design and Verification Conference United States (DVCon U.S.), sponsored by Accellera Systems Initiative, is now accepting abstract submissions for its conference to be held February 29-March 3 at the DoubleTree Hotel in San Jose, California. Abstracts are being solicited for presentations that are highly technical in nature and reflect actual experiences, as well as the emerging trends in using languages, standards, methods and Electronic Design Automation tools. Deadline for submissions is September 10, 2015.

The primary focus of DVCon U.S. is on the practical use of specialized design and verification languages such as SystemC, SystemVerilog and e, assertions in SVA or PSL, as well as the use of AMS languages, design automation using IP-XACT and the use of general purpose languages C and C++.

Submissions are encouraged but not limited to areas such as: System-level Design; Verification and Validation; IP Reuse and Design Automation; Mixed-Signal Design and Verification; and Low Power Design and Verification. Extended abstracts should be between 400-500 words and a maximum of two pages. For more information on the suggested topics and submission guidelines, please visit http://www.dvcon.org/call-extended-abstracts.

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an industry consortium dedicated to the development and standardization of design and verification languages. DVCon currently has three conferences around the globe: DVCon U.S., DVCon India and DVCon Europe. Follow @dvcon on Twitter or to comment, please use #dvcon.

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